The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure containing a graded buffer layer material stack in which a lattice matched epitaxial oxide interlayer is disposed between each semiconductor layer of the graded buffer layer material stack.
Graded buffer layers (GBLs), also referred to as strain relaxed buffer layers (SRBs), are currently one of the front up approaches for 7 nm node and beyond technologies, enabling, for instance, dual channel material FinFETs in the same substrate. As an example, a topmost silicon germanium alloy (i.e., SiGe) of a GBL can be used for growing tensily-strained silicon (Si) channels for n-channel field effect transistors (i.e., nFETs), and compressively-stained germanium or high-germanium percentage SiGe channels for p-channel field effect transistors (i.e., pFETs).
One of the biggest challenges with the process device yields of conventional GBLs is that the defect density at the surface of the GBL is in the 1×105 range even for the best known structures. This level of defect density is far too high to achieve high performance CMOS fabrication. As such, a method is needed in which GBLs can be formed in which the defect density at the surface of each GBL is reduced to allow the GBLs to be employed in high performance CMOS fabrication.